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# Created by write_sdc on Wed Jun  7 16:23:50 2023

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set sdc_version 1.9

set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA
set_operating_conditions typical -library typical
set_wire_load_mode top
set_wire_load_model -name smic18_wl10 -library typical
set_max_area 0
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[79]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[78]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[77]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[76]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[75]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[74]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[73]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[72]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[71]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[70]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[69]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[68]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[67]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[66]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[65]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[64]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[63]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[62]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[61]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[60]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[59]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[58]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[57]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[56]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[55]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[54]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[53]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[52]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[51]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[50]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[49]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[48]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[47]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[46]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[45]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[44]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[43]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[42]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[41]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[40]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[39]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[38]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[37]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[36]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[35]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[34]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[33]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[32]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[31]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[30]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[29]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[28]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[27]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[26]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[25]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[24]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[23]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[22]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[21]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[20]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[19]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[18]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[17]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[16]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[15]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[14]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[13]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[12]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[11]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[10]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[9]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[8]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[7]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[6]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[5]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[4]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[3]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[2]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[1]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
{data_i[0]}]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports          \
data_load]
set_driving_cell -lib_cell NAND2X1 -library typical -pin Y [get_ports key_load]
set_load -pin_load 0.012984 [get_ports {data_o[63]}]
set_load -pin_load 0.012984 [get_ports {data_o[62]}]
set_load -pin_load 0.012984 [get_ports {data_o[61]}]
set_load -pin_load 0.012984 [get_ports {data_o[60]}]
set_load -pin_load 0.012984 [get_ports {data_o[59]}]
set_load -pin_load 0.012984 [get_ports {data_o[58]}]
set_load -pin_load 0.012984 [get_ports {data_o[57]}]
set_load -pin_load 0.012984 [get_ports {data_o[56]}]
set_load -pin_load 0.012984 [get_ports {data_o[55]}]
set_load -pin_load 0.012984 [get_ports {data_o[54]}]
set_load -pin_load 0.012984 [get_ports {data_o[53]}]
set_load -pin_load 0.012984 [get_ports {data_o[52]}]
set_load -pin_load 0.012984 [get_ports {data_o[51]}]
set_load -pin_load 0.012984 [get_ports {data_o[50]}]
set_load -pin_load 0.012984 [get_ports {data_o[49]}]
set_load -pin_load 0.012984 [get_ports {data_o[48]}]
set_load -pin_load 0.012984 [get_ports {data_o[47]}]
set_load -pin_load 0.012984 [get_ports {data_o[46]}]
set_load -pin_load 0.012984 [get_ports {data_o[45]}]
set_load -pin_load 0.012984 [get_ports {data_o[44]}]
set_load -pin_load 0.012984 [get_ports {data_o[43]}]
set_load -pin_load 0.012984 [get_ports {data_o[42]}]
set_load -pin_load 0.012984 [get_ports {data_o[41]}]
set_load -pin_load 0.012984 [get_ports {data_o[40]}]
set_load -pin_load 0.012984 [get_ports {data_o[39]}]
set_load -pin_load 0.012984 [get_ports {data_o[38]}]
set_load -pin_load 0.012984 [get_ports {data_o[37]}]
set_load -pin_load 0.012984 [get_ports {data_o[36]}]
set_load -pin_load 0.012984 [get_ports {data_o[35]}]
set_load -pin_load 0.012984 [get_ports {data_o[34]}]
set_load -pin_load 0.012984 [get_ports {data_o[33]}]
set_load -pin_load 0.012984 [get_ports {data_o[32]}]
set_load -pin_load 0.012984 [get_ports {data_o[31]}]
set_load -pin_load 0.012984 [get_ports {data_o[30]}]
set_load -pin_load 0.012984 [get_ports {data_o[29]}]
set_load -pin_load 0.012984 [get_ports {data_o[28]}]
set_load -pin_load 0.012984 [get_ports {data_o[27]}]
set_load -pin_load 0.012984 [get_ports {data_o[26]}]
set_load -pin_load 0.012984 [get_ports {data_o[25]}]
set_load -pin_load 0.012984 [get_ports {data_o[24]}]
set_load -pin_load 0.012984 [get_ports {data_o[23]}]
set_load -pin_load 0.012984 [get_ports {data_o[22]}]
set_load -pin_load 0.012984 [get_ports {data_o[21]}]
set_load -pin_load 0.012984 [get_ports {data_o[20]}]
set_load -pin_load 0.012984 [get_ports {data_o[19]}]
set_load -pin_load 0.012984 [get_ports {data_o[18]}]
set_load -pin_load 0.012984 [get_ports {data_o[17]}]
set_load -pin_load 0.012984 [get_ports {data_o[16]}]
set_load -pin_load 0.012984 [get_ports {data_o[15]}]
set_load -pin_load 0.012984 [get_ports {data_o[14]}]
set_load -pin_load 0.012984 [get_ports {data_o[13]}]
set_load -pin_load 0.012984 [get_ports {data_o[12]}]
set_load -pin_load 0.012984 [get_ports {data_o[11]}]
set_load -pin_load 0.012984 [get_ports {data_o[10]}]
set_load -pin_load 0.012984 [get_ports {data_o[9]}]
set_load -pin_load 0.012984 [get_ports {data_o[8]}]
set_load -pin_load 0.012984 [get_ports {data_o[7]}]
set_load -pin_load 0.012984 [get_ports {data_o[6]}]
set_load -pin_load 0.012984 [get_ports {data_o[5]}]
set_load -pin_load 0.012984 [get_ports {data_o[4]}]
set_load -pin_load 0.012984 [get_ports {data_o[3]}]
set_load -pin_load 0.012984 [get_ports {data_o[2]}]
set_load -pin_load 0.012984 [get_ports {data_o[1]}]
set_load -pin_load 0.012984 [get_ports {data_o[0]}]
set_load -pin_load 0.012984 [get_ports encry_ok]
create_clock [get_ports clk]  -period 8  -waveform {0 4}
set_clock_uncertainty 0.5  [get_clocks clk]
set_input_delay -clock clk  4.8  [get_ports {data_i[79]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[78]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[77]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[76]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[75]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[74]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[73]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[72]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[71]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[70]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[69]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[68]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[67]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[66]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[65]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[64]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[63]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[62]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[61]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[60]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[59]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[58]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[57]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[56]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[55]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[54]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[53]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[52]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[51]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[50]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[49]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[48]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[47]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[46]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[45]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[44]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[43]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[42]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[41]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[40]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[39]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[38]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[37]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[36]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[35]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[34]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[33]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[32]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[31]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[30]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[29]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[28]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[27]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[26]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[25]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[24]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[23]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[22]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[21]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[20]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[19]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[18]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[17]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[16]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[15]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[14]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[13]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[12]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[11]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[10]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[9]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[8]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[7]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[6]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[5]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[4]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[3]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[2]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[1]}]
set_input_delay -clock clk  4.8  [get_ports {data_i[0]}]
set_input_delay -clock clk  4.8  [get_ports data_load]
set_input_delay -clock clk  4.8  [get_ports key_load]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[63]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[62]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[61]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[60]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[59]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[58]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[57]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[56]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[55]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[54]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[53]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[52]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[51]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[50]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[49]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[48]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[47]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[46]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[45]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[44]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[43]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[42]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[41]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[40]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[39]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[38]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[37]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[36]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[35]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[34]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[33]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[32]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[31]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[30]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[29]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[28]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[27]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[26]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[25]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[24]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[23]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[22]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[21]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[20]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[19]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[18]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[17]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[16]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[15]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[14]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[13]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[12]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[11]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[10]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[9]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[8]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[7]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[6]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[5]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[4]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[3]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[2]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[1]}]
set_output_delay -clock clk  -max 4.8  [get_ports {data_o[0]}]
set_output_delay -clock clk  -max 4.8  [get_ports encry_ok]
